liweiwei90

add opcodes for zc extensions v0.70.3

3

The spec for zc extension(version 0.70.3) can be found in [zc spec](https://github.com/riscv/riscv-code-size-reduction/releases/tag/v0.70.3-TOOLCHAIN_DEV)

add support for rve

4

This PR adds support for rve, if rve is enabled: * disable the handling of upper registers * change the syscall number to register t0

add support for cbo.zero in CMO extensions

13

Currently, the cache block size is assumed to be two times of xlen.

add support for Zicbo* extension

1

this PR will add support for Zicbo* extension. It also add BLOCKSZ macro which will be used by tests for cbo.zero. The cache block size can be configured by riscv-config...

What's the difference between "RV32 only" and "*XLEN=32 only"

9

In current privilege spec, most upper half CSRs are described as "RV32 only". But htimedeltah is described as "HSXLEN=32 only", and mseccfgh is described as "RV32 only" and "MXLEN=32 only"...

Something wrong for the fields of upm/mpm/spm/vspm CSRs in zjpm-spec.pdf: 

add support for cmo extension

26

add support for cmo extension: - add parameter for cache block size - add cbo.zero to zero the cache block - add cbo.inval/flush/clean to do envcfg csr and memory access...

[RFC] make XLENs changable

16

This patchset add the support for changable XLENs: - Instruction functions use different XLENs for different privilege modes - Make *XL field of *status CSRs writable - The length of...