liweiwei90
liweiwei90
> Ack, but we won't merge this until it is clear the encodings won't change. OK. I'll update this if the encodings changes
The base address for jump table is JVT[31:6] with 000000, not simple JVT[31:6].
@aswaterman Thanks for your explanation. However, I still have some question: - As most of the length of CSRs for different modes is related to the XLEN for that mode....
> * The currently active XLEN is the one that matters, so HSXLEN is not relevant in M-mode. The full `henvcfg` is accessed, and `henvcfgh` is illegal. However, the length...
Thanks for your clarification. If henvcfgh/htimedeltah will exist only when the _current_ XLEN == 32 instead of HSXLEN == 32, do you mean the length of other *XLEN CSRs will...
The default DRAM_BASE is 0x80000000. You can specify memory layout by "-m" option.
Sorry for late reply. I didn't find any spec to write this. I just found this in a closed issue(https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/11). > Is there an RVE ABI that specifies the syscall...
> OK, I propose we leave this PR open until there is a written RV32E syscall ABI. OK.
I know this check which is done by require_vector_vs. However, the vector instructions have many other checks. What I really mean is whether dirty_vs_state should be called when the other...