Thach Nguyen

issues with deep_pi_car.py

1

I followed this great tutorial step-by-step, and I really appreciate the author for making this project available to public. I run the command ```python3 deep_pi_car.py``` and got this error: ```...

tlu_flush_path_e4

7

Can someone help me understand this snippet of code from `dec_tlu_ctl.sv`? I am not familiar with the naming convention of the SweRV core either, so I would also appreciate if...

./configure option

10

how should I configure the make file for RISCV? Thanks

Debug Module did not become active. dmcontrol=0x0

2

I implemented SweRV_EH1 on a Zedboard fpga. I am trying to use openOCD and Jtag Arm-USB-Tiny_H to download code to the board as instructed in the README. I have checked...

c compiler cannot create executable

2

 I installed my gcc-riscv64-unknown-elf through apt-get "install gcc-riscv64-unknown-elf" I tried update build-essential and many other pkgs, but it still spits out this error. Does anyone have suggestion?...

tutorial on adding new instructions to RISCV ISA?

2

Does anyone know how to add new instruction to RISCV ISA? I researched online but did not find good detailed/step-by-step on how to. Thanks

RTL simulation

1

Hello! Does this repo support RTL simulation like Verilator? Thanks in advance

Debug Module did not become active. dmcontrol=0x0

1

I implemented SweRV_EH1 on a Zedboard fpga. I am trying to use openOCD and Jtag Arm-USB-Tiny_H to download code to the board as instructed in the README. I have checked...

Routing issue when implement SweRV Core in Zedboard

1

Hello, I tried to implement the SweRV Core in Zedboard fpga and ran into a routing issue when run implementation. The issue is as below: ``` [Place 30-574] Poor placement...