Keegan Dent

byteinvert function

3

I needed to change bit-endianness of a byte-stream and it took a little while to figure out what _seems_ to be the simplest way to do this. Maybe it could...

I'm using the vivado backend initialized with the following code block ```python backend = get_edatool(tool)(edam=edam, work_root=proj_path, verbose=False) ``` The `verbose=False` seems to have no effect because of [these](https://github.com/olofk/edalize/blob/6114cbf6e6feb96d3cc699e9e452665cc0df7934/edalize/edatool.py#L466) [lines](https://github.com/olofk/edalize/blob/6114cbf6e6feb96d3cc699e9e452665cc0df7934/edalize/edatool.py#L470). There...

Vivado flow not re-run when Verilog parameter is changed

5

With the way the current Makefile is written, Synthesis, Implementation, etc. are not re-run when a Verilog parameter is changed in the `edam`. This is because the `.xpr` file is...

right alignment behavior

10

I've been strugging with a communication system that expects the bitstream to be "right-aligned". Basically the idea is to perform zero-padding on the left instead of the right. I also...

Implementing buffer with `axis_fifo` or `axis_pipeline_fifo`

2

These modules are incredibly useful, but I'm a little unclear as to which of the two makes sense for a buffer. (I think what I want is a skid buffer,...