Krzysztof Boroński
Krzysztof Boroński
#### Description ##### DEPENDS ON #1999 (I will rebase this branch to exclude commits from #1999 once it gets merged). Parse XDC placement constraints using TCL interpreter. * `libtclcpp` -...
Flow configuration from `flow.json` were not overriden by options passed by CLI. This PR fixes that. Additionally, it allows to override a path with an empty string/None. This is useful...
The synth module is quite troublesome, because its outputs are dependent on the contents of a Tcl script used by Yosys. This PR is an attempt to solve this issue...
Add support for nextpnr. Nextpnr can be compiled into different variants, which can have their own variant-specific options. This seems to map rather nicely into class inheritance, so in this...
Adds flow, synthesis script and part list for ice40. Tested on FOMU (pvt) (see https://github.com/chipsalliance/f4pga-examples/pull/337). Depends on #585 and #581.
This issue accumulates various ideas for improvements related to f4pga (CLI tool) that was recently merged (#530). Please refer to https://f4pga.readthedocs.io/en/latest/f4pga/Usage.html and related pages for documentation of this new tool....
This example uses the f4pga python package to create a bitstream for ice40 using a yosys+nextpnr flow. The example code is meant to be used on a FOMU (pvt) board....
First described in [#554](https://github.com/chipsalliance/f4pga/issues/554) This behviour forces the user to run f4pga with PWD being equal to the location of flow.json. Otherwise, the paths in flow.json would be resolved incorrectly.
Adds a python script that inspects f4pga flows and generates rst files as part of documentation.
AST for accessing value seems to get cloned for read and write access for pre/post incremenatation and decrementation operations. This results in any side-effects that could be present in the...