Qiaoyi(Joey) Liu

Add a Custom Name for CoreIR Generator When Generate Verilog

14

I am using coreIR to generate a memory placeholder in RTL for further power analysis. I want the RTL module which coreIR generator generated have the specific name matching with...

add verilog customized name for generator

2

I made some changes to the verilog analysis passes and it work for me for the issue. https://github.com/rdaly525/coreir/issues/941

Support Interpreter Simulation Plugin in PycoreIR

2

Dillon has helped us create a simulation plugin in the coreIR interpreter to simulate the unified buffer functional model with PE and other logic. Is that possible to have pycoreir...

https://github.com/dillonhuff/clockwork/blob/5c41205e8ec0e6dafb357373ec4d70688baa1896/example_progs/matmul.cpp#L57-L58

Hi Dillon@dillonhuff , Jeff and I are testing a version of camera pipeline with intermediate buffer generated in the demosaic stage. We also unroll the x dimension by 2 to...

FFT Breaks Ratematched Scheduler

1

I am encountering the following error when running garnet single port scheduling on the fft app. ``` clockwork: app.cpp:821: std::pair extract_linear_rational_approximation(isl_aff*): Assertion `div_dims == 1' failed. ``` I think it's...

comment out upsample for `isca_program()` https://github.com/dillonhuff/clockwork/blob/28e80b13dfcb463c235ad85bf57131ca759a25ff/build_set_test.cpp#L17485

9f319f5 is the first bad commit commit 9f319f5 Author: Jeff Setter [email protected] Date: Sun Nov 22 11:02:32 2020 -0800 Fix unsharp kernel values Unsharp break after this commit in master

Currently all backend memory module is migrated to cgralib. cwlib will not be used in the future. The current laketile is renamed to cgralib.mem_amber and it will be remapped to...