Qiaoyi(Joey) Liu comments

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                                            Qiaoyi(Joey) Liu

Add a Custom Name for CoreIR Generator When Generate Verilog

@rdaly525 Any update on this feature? I found the name is too long for some circumstances.

Add a Custom Name for CoreIR Generator When Generate Verilog

Thanks Lenny. It does not work for me. In the verilog generated from coreIR, the name of that module is not override by the `verilog_name`. Do I need to change...

Add a Custom Name for CoreIR Generator When Generate Verilog

Yeah, I think the difference between module and generator may affect. I print out the meta-data in that instance and it's empty. I push my code in the `unsharp_fix` branch...

Add a Custom Name for CoreIR Generator When Generate Verilog

@rdaly525 Thanks for the suggestion. I try both way but none of them generate the corresponding name in verilog. Should the `Generator*` and `Module*` variables used somewhere in the code?...

Add a Custom Name for CoreIR Generator When Generate Verilog

No. I only see those instances of memory tile in the json. Should I add the rungenerator passes while save the json?

Add a Custom Name for CoreIR Generator When Generate Verilog

It seems that if I dump the metadata in module or generator, the metadata will be lost when I save the top level into json. I currently use the json...

Support Interpreter Simulation Plugin in PycoreIR

Any suggestion is welcome. @dillonhuff @David-Durst @leonardt

FFT8 doesn't pass memory mapper

This is supposed to be a banking issue. Which branch are you in and what's the command to reproduce this issue?

build/make problem

Did you source the user settings? https://github.com/dillonhuff/clockwork#setting-your-private_settingssh

New lake rate match

@Ritvik1sharma Can you recreate a PR to merge your branch into `new_lake` branch?