John's Brew

Thanks for your quick answer @seldridge, I drafted this report a few weeks ago, convinced that this issue could be solved very simply, however it seems I overlooked it. Thanks...

Hi @HaibaraMegumi Thank you for your interest in sv2chisel and for your bug report. I have just realized there is no test-cases involving macros (we have migrated our code-base to...

Just pushed 0.5.1-SNAPSHOT with very minimally improved support for preprocessing macros. See https://github.com/ovh/sv2chisel/commit/c0cfcd0153750cecb7c14b5109ab627a0271cad1 This won't unfortunately solve the underlying deficient support for macros but at least you should be able...

Hi @Soya-Onishi Sorry for this late answer, I missed the notification...! I am quite sorry to read a definite answer about this, @jackkoenig to answer your comment: > what does...

Nice hack @dbear496 It's a great use of `when.cond` which has been introduced by https://github.com/chipsalliance/chisel3/commit/cdb7bb27bd675a8a114701b97a45c56e26ef42b5 in January 2021 (a few months after I ran into this issue)

- such an operator should rather be named `:+=` to highlight the actual hardware connection taking place behind the scene - it's fairly easy to provide [a naive user-side implementation...

Hi @sequencer I kind of agree with the underlying issue of `UInt` being often used as default type even where it is not justified. I would like to point out...

> I think return `this.type` is a good way. However there is another issue that: what's the behavior of `|` `^` `&`? they have two operators. Scala cannot decide which...

Hi @chick This "feature" or most likely "design choice" is getting very annoying for testing Ready/Valid interfaces. Consider the following case: ```scala class DumpBufferRegister(width : Int) extends Module { val...

Hi @chick & @ducky64 and thank you for your answers FYI, my current solution consists in wrapping the DUT with a Module that registers all the input signals at posedge....