Dr. med. Jan Schiefer

LaserWeb4 development, Linux, the universe and everything

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LaserWeb4 *seems* to have dropped support for Linux a while ago. This is a major problem for many users, since LaserWeb is the only "serious" laser engraving solution for GRBL...

Nuxt3 rc13: useFetch(...) POST ignoring header Content-Type ( Client side app )

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### Environment RootDir: /home/xxx/yyy 01:48:06 Nuxt project info: 01:48:06 ------------------------------ - Operating System: `Linux` - Node Version: `v18.12.1` - Nuxt Version: `3.0.0-rc.13` - Nitro Version: `0.6.1` - Package Manager: `[email protected]`...

Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys

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SpinalHDL: 1.10.1 Scala version: 2.12.18 sbt version: 1.9.8 SymbiYosys version: Git 19.02.204 Problem: - SymbiYosys chokes on "assert(xxx) else begin end"- statements ( maybe not supported? ) - also, a...

Closes # https://github.com/SpinalHDL/SpinalTemplateSbt/issues/39 https://github.com/SpinalHDL/SpinalHDL/issues/1314 # Context, Motivation & Description - SymbiYosys multiclock mode has to be used when using ResetKind == ASYNC, so enable multiclock mode when using this reset...

Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now

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See issue https://github.com/SpinalHDL/SpinalHDL/issues/1314 Remove "assert() else begin end"-block generation for now.

WishboneSlaveFactory - doWrite is never called in pipelined mode

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It may be totally possible that I am completely and utterly wrong... but I have been playing with WishboneSlaveFactory and and noticed some odd behaviour: - When driving WishboneSlaveFactory from...

Creating a layout with bare HTML is painful and slow. Objective: Provide support for Material "Layout Grid". ( mdc-layout-grid / mdc-layout-grid__inner / mdc-layout-grid__cell ) and associated attributes.

Feature request: Support Lilygo T-FPGA board with GWU2X USB-to-JTAG bridge

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Hi, I just picked up an interesting and cheap FPGA board - Lilygo T-FPGA with an Gowin GW1NSR-LV4CQN48PC6/15 and an ESP-S3 as an IoT solution. Interestingly this board seems t...

Use multiclock mode in formal verification

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Specify we have async signals / resets in the formal verification configuration with SpinalFormalConfig( _hasAsync = true ) . This works for SpinalHDL 1.10.1. With the newer SpinalHDL versions (...

SpinalHDL: 1.10.1 Scala version: 2.12.18 sbt version: 1.9.8 SymbiYosys version: Giit 19.02.204 Problem: - when using a async reset in your design you generate Verilog like "always @(posedge clk or...