Dr. med. Jan Schiefer
Dr. med. Jan Schiefer
Ok, why not. Unfortunately I don´t have much experience with the AppImage ecosystem (and also I am a physician in COVID-19 stress). However, Linux and CNC is my hobby for...
Trying to build the AppImage. I'm having the LaserWeb4 and lw.comm-server in parallel directories. (...) packaging for linux x64 using electron 2.0.18 to dist/linux-unpacked Unhandled rejection Error: Exit code: 1....
Ok. I have created working builds of the latest git version of LaserWeb4 for Linux x64 and Windows x64 with a little hacking: https://drive.google.com/open?id=1oGcQKB0K32n3B7irCJjCIg7AIyqRk-hz - I removed all references to...
I'll try to create a patch for the build problems in the next few days. How can I submit the patch?
Can you provide an example on how you fixed his?
Do you speak Mandarin? ... https://cdn.gowinsemi.com.cn/UG1003.pdf
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
The line is necessary to get a purely synchronous reset in this context. Without this line, the following code is generated: ``` (...) always @(posedge clk or posedge reset) begin...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
Yes this actually works in SYNC reset mode. In ASYNC reset mode we actually need to set the SymbiYosys multiclock mode. Here my attempt to fix both issues: https://github.com/SpinalHDL/SpinalHDL/pull/1320 -->...
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
Not yet...ok. Well, the assumeResetReleaseSync / assumeIOSync2Clock in this complex example make sense... --> I need to implement this in the SpinalHDL Template, so the template formal workflow works again...