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                                            iksw

Vicuna I$ compliation error when Memory Width and Way Length are same

I also see that both tag and data memories are implemented as flops with dual port memory interface. Just suggesting if that can be changed to single port memory interface.

How do I disable I$ parallel memory request whenever there is a branch and it's a tag hit?

EDA tool and version: Verdi Operating system: Linux Version of the Ibex source code:[c9e3fde]

How do I disable I$ parallel memory request whenever there is a branch and it's a tag hit?

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