Hossein Askari

Previously, I had my own hdl wrapper :D but then I decided to use fusesoc since I believe it is much mature than what I have. In my build setup,...

I am trying to use this IP with FuseSoc and everything seems to be working. However, I want to use `axi_driver` in `axi_test` package in my test bench but it...

[HW] Adding support for Fixed-Point vector instructions

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Description of PR that completes issue here... ## Changelog - Support for Fixed-Point vector instructions: `vaadd, vaaddu, vsadd, vsaddu, vssub, vssubu, vasub, vasubu` - Two status register for fixed-point unit:...

Instruction for chisel3 users

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I added instructions for those who are using chisel3. With the current setup, the sbt publish command results in the following error: check] ValExec_fNFromRecFN.scala:44: Chisel3 compatibility: io's should be wrapped...

[HW] Draft PR for Implementing Ara on FPGA

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This is a **Draft PR** for FPGA implementation of Ara. There are several issues that needs to be discussed before merging this PR into main branch: - As it can...

Using fusesoc, I am not able to import axi.core to my project properly. I was getting this error: `# ** Error: ../src/pulp-platform.org__axi_0.38.0/src/axi_test.sv(1285): (vlog-2164) Class or package 'rand_id_queue_pkg' not found.` I...

RISC-V tests are not passing. At the end of each risc-v test, we should see `OK\n` or `ERR\n` in register `a0-a3`. Right now, these registers are not modified throughout the...

Lets use FuseSoC: - The entire project folder is re-structured - Added a simple FuseSoC core file - Updated README

- Using riscv64 compiler - Using gtkwave to view simulation waveforms

Since last release, BARVINN documentation has not been updated. The following needs to be added: - The new APB bus for MVU PITO. - C runtime for PITO. - AXI...