hlide

One possibility is to transform: - Z80_MREQ and Z80_RD into one flag Z80_MRD - Z80_MREQ and Z80_WR into one flag Z80_MWR - Z80_IOREQ and Z80_RD into one flag Z80_IORD -...

Just for your information, I built a MCLZ8 (https://github.com/MicroCoreLabs/Projects/tree/master/MCLZ8) but I stumbled about some obstacles which made the MCLZ8 firmware a bad Z80 emulator (especially if you want to be...

Case of near JMP: ``` { ICLASS : JMP CPL : 3 CATEGORY : UNCOND_BR EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0xE9 not64 BRDISPz() OPERANDS :...

FYI, sizeof(int) != sizeof(ssize_t) in 64-bit environment: in AMD64, it will issue more lengthy instructions (64-bit operation on register needs an instruction prefix while 32-bit operation doesn't) for no big...

@cameron314: as long as the instruction cache can absorb those extra bytes, it won't. Suppose that all the code of a big program was using 'int' and was fine in...

@cameron314: _off-topic_ I'm quite interested with your free-lock SPSC and MPMC queues implementations, but I have a question. I need a free-lock MPSC queue and I was wondering how to...

The CRC errors are totally reproductive and have the same values. I also tried with a full 64KB RAM ($0000-$FFFF) but same result so far. I have no reason to...

So I tried: 

Sorry, I was on holiday and a very bad news occurred so I was not inclined to come back here until a certain moment. Might you add the change you...

So getting back to your last source and just adding ZEXALL and make it running in mode 3 with full 64KB RAM and loading ZEXALL in RAM in setup, I'm...