hlide

@buraktamturk One year ago I found [HAXM](https://software.intel.com/en-us/forums/android-applications-on-intel-architecture/topic/507158)(the last post in this thread is mine) and [a GitHub project as a sample how to use HAXM](https://github.com/Nukem9/Haxm) but the sample was so...

@rianquinn I have. But it raises more questions. First, is there any version running in Windows as a host? Second, it appears to use mingw64 and gcc. is it just...

@rianquinn I guess I can also post my question in https://github.com/Bareflank/hyperkernel? My main question is: can a hypervisor intercept an external event like an interrupt which needs to be executed...

@rianquinn oh and "and the hypervisor is built with Clang": does it mean i still need to use something else VS for compiling the emulator program supposedly that what you...

So far as I know, your ISA is based on a two-register form (register file with 1 read port and 1 write port). If you plan having a three-register form...

Ok, there is one thing you must observe if you are trying to mimic a true hardware CPU. That register file I was talking about is a very important thing...

take a look at https://github.com/Domipheus/TPU/blob/master/isa/TPU%20Instruction%20Set%20Architecture.pdf. It is a good example of 16-bit CPU ported to hardware and so aware of the hardware limitation.

`JMP V`: if relative branch, you could place your code anyway unlike the actual version.

The actual `JMP V` jumps to an absolute address between |0..4095], right? so you're condemning the access of the code beyond 4095 whereas your memory is between [0..65535]. If you...

It would be great to have a conditional relative branching as well because most loop kernels (the thing being iterated several times) are in the local scope of a relative...