hlide

Results 17 issues of hlide

My project can use several displays and an SSD1306 OLED display is not mandatory. But if I try to call the `begin` method, it freezes my firmware as I use...

For instance: ``` { ICLASS : JMP CPL : 3 CATEGORY : UNCOND_BR EXTENSION : BASE ISA_SET : I86 ATTRIBUTES: MPX_PREFIX_ABLE PATTERN : 0xE9 not64 BRDISPz() OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP...

I see no other way for discussing how it may be possible for SimpleVisor to run dynamic recompiled code emulating non-x86-64 code. I have written an emulator which runs some...

There is a different way to use stack (supposedly it resides somewhere in memory). ``` push a push b push c ``` can be done this way: ``` sub sp,...

Not a proposal, not an issue, just a way to show a different ISA which tries to use as much as possible all the field bits of an instruction. This...

This simple _strlen_ implementation for Allegrex: ``` 89014c4: move $v1, $a0 89014c8: lb $v0, 0($v1) 89014cc: bnez $v0, 0x089014C8 89014d0: addiu $v1, $v1, 1 89014d4: nor $v0, $zr, $a0 89014d8:...

need info

Most compilers allow to insert special instructions through intrinsic functions. This is a way to avoid having .asm files and a good way to help the compiler to be aware...

enhancement
question
need info

I may plan to add a new architecture instead of using the current MIPS architecture which is a work in progress. because ALLEGREX is not recognized by capstone framework and...

need info
waiting for pull req

https://github.com/floooh/chips/blob/05cd84e43a1070a16c4edbcaa53a761561b629b8/codegen/z80_gen.py#L342 This line looks incorrect for me. Let me take an example. SHARP MZ-700 has an LSI which handles PAL/NTSC video circuit and also decodes address bus for dispatching between...

Source at https://github.com/intelxed/xed. Version 3. XED being a complete encoder/decoder for every architecture including AMD, KNC, KNL. For instance, it can give details on some unofficial instructions: ``` { ICLASS...