Muhammad Hadir Khan

@tamood if you look at line 36 of `RocketTile.scala` it has two statements: ``` require(icache.isDefined) require(dcache.isDefined) ``` failing to fulfil this requirement bombs the build process.

Which means there is not yet any support to build a more tiny or nano version of the core that does not even have caches inside.

@jamesdunn I followed the first step of debugging by downloading OpenOCD from Sifive's website. Upon running openocd from there like the following command: ``` ./bin/openocd -f share/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg -f ``` I...

So I flashed the .mcs file available from SiFive's website and it runs fine since I can see the SiFive logo on the UART terminal and a blinking RGB LED....

Update: Not connecting the `nRST` (grey jumper) to the JD PMOD Pin 9 and the `nTRST` (orange jumper) to the JD PMOD Pin 2 removes the abnormal behavior (RGB LED...

No @alonamid that answer was based on the **release: 1.3.0**. This release has a different configuration for the `L1ScratchpadRocketConfig` i.e it has separate ICache and DCache configured as scratchpad memories....

Hi Jerry, Is there a config or adjustment with which I can completely remove the caching protocol and use small on-chip srams for instructions and data storage? I am looking...

@jamesdunn @jerryz123 anyone looking into this problem?

No I built it on the same OS, in-fact I also downloaded the already prebuilt binaries of OpenOCD and RISCV GNU Toolchain from the SiFive website. My Ubuntu version is:...

Thanks @jamesdunn for looking into this matter. Yes, I was looking at the flash implementation on `freedom` and was thinking of doing a mimic on the Chipyard, however, I didn't...