Dan Petrisko

verilog_defaults doesn't work with systemverilog plugin

2

Hi, not sure if this the right place to ask. I'm trying to use the systemverilog plugin for yosys, but I'm having trouble with include paths. The UHDM frontend doesn't...

Assertion failure expected?

2

Hi, I'm trying to use the pulp debug module for my own chip. Things seems to be mainly working, but I'm trying to sort out the last few bugs. I'm...

Support for 'inside' with parameter arrays

5

Hello, I'd like to request support for using 'inside' with parameter arrays. Trying the following example ``` module foo #(parameter int checklist_p [2:0] = '{0, 1, 2}) (); localparam pass_lp...

This PR adds support for BlackParrot simulation to OpenPiton via the BYOC framework. OpenPiton+BlackParrot on FPGA is currently beta (read: broken =)). WIP until the FPGA version works or we...

Bitmanip?

2

Hi, are there plans (/ private branches) with tests for Zba, Zbb, Zbc, Zbs? Thanks!

FP instructions not modelled?

3

I'm trying to track floating point unit usage in zsim. In decoder.cpp, I see ``` /* FP, SSE and other extensions */ case /*XC(X)87_ALU*/ XC(X87_ALU): //emitBasicOp(instr, uops, 1, PORTS_015); break;...

Verilator fails test_dff.py example

4

Hello, the default example fails in Verilator (5.022, though it shouldn't matter). ``` # test_dff.py import random import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge from cocotb.types import...

Fix XLEN assumption in riscv_instr_pkg

2

This assumption causes an unaligned store on 64b processor in some cases. This fix should preserve behavior on 32b processors but allow for aligned 64b store

Mismatch between yosys-synlig and bsg_sv2v

2

Hi, I am trying to synthesis a systemverilog design with synlig (https://github.com/dpetrisko/tt07-dll/tree/main). With the plugin installed from main, the design is able to parse and synthesize to completion. Unfortunately, the...

systemverilog-plugin: Blackparrot support (was: ERROR: Failed to detect width for parameter)

45

Hi, trying to track down an issue, I believe it's in the plugin but it could also be in surelog. I am using the default submodules except for https://github.com/chipsalliance/yosys-f4pga-plugins/pulls/377 to...