Dan Petrisko comments

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                                            Dan Petrisko

Slack Invite

[email protected] Tons of programming experience, decent android dev.

verilog_defaults doesn't work with systemverilog plugin

Thank you!

Assertion failure expected?

Oh, I hadn't noticed that opentitan patches the pulp DM with different primitives, so it's not standard. My mistake! Which version of Openocd do you suggest? I just pulled down...

Support bind statements within generate blocks

Hi @wsnyder, could you post the testcase and a link to the WIP patch on this issue? Not sure if we’ll be able to take a look for a bit,...

Bitmanip?

For what it's worth I ended up setting up the bitmanip compliance tests at: https://github.com/riscv-non-isa/riscv-arch-test to

Virtual memory support

Hi, curious if this ever became supported. Thanks!

ASIC implementation for verilog-ethernet

Hi @alexforencich, we've been plugging away at this. We've gone all the way to tape-in (everything except sending it out) with the goal of taping out sometime this year! The...

rv64gc failing spike due to exception trap_store_address_misaligned

May be related to this? https://github.com/chipsalliance/riscv-dv/pull/925

Fix XLEN assumption in riscv_instr_pkg

Hi can someone take a look at this?

Using spike in a lock-step hardware simulation

Hi, is there any update on upstreaming the lockstep simulation? If maintainers would help define a cosim step / trap interface similar to https://github.com/chipsalliance/dromajo/blob/master/src/dromajo_cosim.cpp, I'd be happy to help push...