Anthony Donlon
Anthony Donlon
**Problem description** Could you change the color of the 'Stage All' button on the summary page from red to green? Because it's relatively not a dangerous action than 'Discard All'...
The following example fails if `--lint-only` and `--debug-check` is on. ``` SystemVerilog interface my_if #( parameter integer DW = 8 ) (); if (DW < 4) begin: gen_blk // under...
Fixes #4497 Fixes #3858 Requires: #4581, #4582 Probably fixes: #3875, #4013 ## Backgrounds #4497 fails because `uvm_sequencer#(uvm_sequence_item)` and `uvm_sequencer#(uvm_sequence_item, uvm_sequence_item)` are treated as different parameterization of class uvm_sequencer, but they're...
Hi, In V3Param, when the param processor encounters reference to parameterizable classes without parameter overrides, it copies the original AstClass node and use the uncopied one as the class instance,...
It's similar to #6 but for the desktop version
This PR support size prefix for `%t` in strings. So strings that contain `%0t` formatting specification can be parsed correctly.
Hi, this patch fixes the errors when building with MinGW toolchain (x86_64-w64-mingw32) ``` ../src/flash/nor/rp2040.c: In function 'rp2040_lookup_rom_symbol': ../src/flash/nor/rp2040.c:192:15: error: unknown type name 'uint'; did you mean 'u_int'? 192 | const...
## ❓ Questions and Help ### What is your question? 当在 AutoModel 不传入 VAD 模型名,以禁用 VAD 时,输出的文本是未分句的原始输出。但理论上 VAD 应与分句功能独立,禁用后不应影响分句输出才对。 ### Code #### Run w/ vad model ``` Python model =...
Hi, This PR fixes syntax highlighting in some 'automatic' keyword related context. For example ``` SystemVerilog module automatic test_mod; task test(); automatic test_pkg::cls obj; endtask endmodule ``` Before: After: