Donggyu Kim
Donggyu Kim
There's a related thread in Google Group: https://groups.google.com/forum/#!topic/riscv-boom/yxDwmpjtQrE In Berkeley, we also think it's a very important problem, so start hunting a solution.
C++ simulators cannot be compiled with comb loops.
Did you try it with the latest master? It should tell you problematic wires. Please refer to #339
@colinschmidt Can you confirm this works?
For now, it's impossible with verilator, but you may be able to peek/poke with path names of those signals with vcs.
I have a temporary solution for this, but not sure it'll meet your requirements: https://github.com/firesim/riscv-fesvr/tree/windows To handle `addr_t`, you can give `-D__addr_t_defined` to gcc.
For 1, I think we should wait until firrtl 1.2 is released. For 2, I don't see those issues with rocketchip master. How can I reproduce it?
We should update the firrtl files in the test later.
Seems no, so I'm working on it.
5 cycles. But, I believe this is due to: https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/lane-ctrl.scala#L66 If its value is greater than `nSlices`, it'll unexpectedly fire. I actually got this assertion at the beginning of simulation:...