Peek/Poking FIRRTL-generated IO

[shunshou]

I'm trying to have FIRRTL automatically generate a scan chain when a "scan" bundle is included in my design.

Scan bundle = list of signals I want to have custom values for.

But since the added scan signals (scan clk, enable, in, out) are not part of the original Chisel code, there's no way I can test it via the usual peek, poke mechanisms... any idea if there might be some workaround?

[donggyukim]

For now, it's impossible with verilator, but you may be able to peek/poke with path names of those signals with vcs.