David Harris

It would be helpful to add the timeout option to section 4.7. I couldn't find it elsewhere in the docs, and I was getting a timeout error compiling on a...

The testlist docs suggest using the command riscof testlist --config=config.ini https://riscof.readthedocs.io/en/stable/testlist.html However, --suite and --env are now required arguments as well. The example should be updated to match. $ riscof...

Verilator performance issue

11

Verilator is running my RISC-V processor testbench almost two orders of magnitude more slowly than commercial simulators. I've been told that Verilator is as fast or faster than commercial simulators...

Verilator $sscanf reads into array with a delay

3

I am experiencing strange behavior when trying to read lines from a file into an array one at a time. The file has three lines: 10 11 12 When I...

Is a hart a hardware thread?

19

My colleagues and I are struggling to precisely define "hart" and are concerned the spec is misleading. Section 1.1 paragraph 2 states "A RISC-V compatible core might support multiple RISC-V-compatible...

Slow build with GCC 12.2

2

riscof runs normally for me with GCC 11.x installed. It's slow but usable. I've been trying to upgrade to GCC 12.2 (specifically 2023.01.31). riscof appears to hang at INFO |...

Zbkb, Zbkx, Zk* need to be able to be instantiated independently of Zb*

5

As far as I can tell in a brief code review, Zbkb requires Zbb to instantiate the zbb module. Each of these extensions should be independent, and instantiate no more...

Testfloat on Verilator not progressing

4

I started writing sim-testfloat-verilator. It now compiles but seems to hang in the first test. harris@chips:~/cvw/sim$ ./sim-testfloat-verilator harris@chips:~/cvw/sim$ time obj_dir/Vtestbenchfp Running ui32_to_f128_rne.tv vectors ...(no progress)

postproduction line 158 appends 2 zeros to FmaShiftIn. Can they be moved around to make this simpler? See also the zeros in shiftcorrection