David Harris

I'd like to use these files too, as a basis for Q and Zfh tests. Looks like @pawks generated the F tests June 17, 2022. Are the .cgf something you...

Thank you. This is helpful to define a hart as "an abstraction of a hardware thread." If I understand this correctly, a this abstraction means that hart could be a...

I think of context switching as saving and restoring the PC, registers, and CSRs. That's a lighter weight operation than migrating VMs around a data center. Does "execution context" refer...

I have a question about flags set by FCVTMOD.W.D in the Zfa extension. Specifically, consider RV32IFD_Zfa running fcvtmod.w.d on an input of 0xC1EE9B7E5FC9EBA4 = -4.10806e9. The integer output is 0x0B240D02....

These tests have been merged into riscv-arch-test. When I tried using them, I had to modify the RV_TEST_ISA and check ISA strings for cbo.zero in the rv32i_m/CMO and rv64i_m/CMO directories...

Sorry to hear that it is a hard fix. Is it easy for lint to emit a warning that Verilator doesn't (or potentially doesn't) handle such code constructs reliably, and...

This is the profiler output. It’s running single-threaded with most of the time in funct nba. I’m not sure how to tie that to specific parts of Verilog code. The...

Took a while, but this is working now. I had been ending simulation with $stop rather than $finish (to keep the GUI open at the end of a Questa sim),...

I've tracked the issue to a difference between binutils 2.37 and binutils 2.39. Disassembling fmadd.d_b15-01 takes 2.2 seconds with 2.37 and 3 minutes 36 seconds with binutils 2.39. See the...

I'm not sure if posting this in riscv-gnu-toolchain is more appropriate. I've posted an issue there. https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188