Andrew Lenharth
Andrew Lenharth
combinatorial cycles are allowed in HW, but prettify verilog is non-deterministically (I think) failing on them. It is also sometimes expanding the xor below to a chain of 3 xors....
Tracking and discussion issue for #3320
It should give a nice error about unhandled operation.
Simple mechanical movement of Bundle and FVector to ODS definition.
Do initialization checking early in the pipeline before transformations.
This reduces multi-muxes with certain patterns of redundancy. This is a very abbreviated version of prime-implicant style coverings. This can change the output value for an out-of-bounds index,
This adds a connect op to the chirrtl dialect. this will be used for most of the connect weirdness, leaving firrtl.connect to handle sanely constrained IR.
`module(input : bundle` should be transformed to `module(output : bundle`