da-steve101

Segmentation fault crashing tester

3

The tester crashed with a segmentation fault Chisel trace is ``` bash [info] Chisel.TestApplicationException: test application exit - exit code 139 [info] at Chisel.Tester.throwExceptionIfDead(Tester.scala:128) [info] at Chisel.Tester.Chisel$Tester$$mwhile(Tester.scala:138) [info] at Chisel.Tester.start(Tester.scala:763)...

Invalid verilog generated with constant idx into ROM

1

With the following verilog, the always @(*) is interpreted as trigger on all input changes. However as there are no inputs, this never triggers. Hence it has the value xxx....

Allow specifying of clock for blackbox module

2

Added arguments to blackbox which are passed through to the module so the clock can be specified in essentially the same way.

``` scala class UserMod( bw : Int ) extends Module { val io = new Bundle { val in = UInt( INPUT, bw ) val out = UInt( OUTPUT )...

Compilation Error when assigning from other clock

4

I am getting an undeclared variable error for the following: ``` scala class UserMod extends Module { val io = new Bundle { val out = UInt( OUTPUT,8 ) }...

Catting a UInt of width 0 leads to strange sim results

1

The catting a UInt of width 0 onto a value causes strange results in c simulation ``` scala class UserMod extends Module { val io = new Bundle { val...

Fixed AsyncFifo so reset not tied to 0

4

Previous logic was ``` if reset = 1 s1_rst = 0 else s1_rst = reset // reset = 0 ``` changed to ``` s1_rst = reset ```

I accidentally mixed UInt and Vec assigns ``` scala class UIntToVecAssign extends Module { val io = new Bundle { val in = UInt( INPUT, 64 ) val out =...

Move emitRef from Verilog to backend

5

Currently not passing the tests as for some test cases are named twice and hence index does not start at 0. Not sure where this is happening, but seems like...

When creating a node literal such as: ``` scala val tmp = UInt(0, 4) val tmpReg = RegInit(UInt(0, 4)) tmp := tmpReg ``` Gives "Real node required here, but 'type'...