da-steve101

I was getting this issue when cmake tried to use python3 instead of 2.7 I change line 38 of CMakeLists.txt from: ``` find_package(PythonLibs REQUIRED) ``` to ``` find_package(PythonLibs 2.7 REQUIRED)...

Sounds good. Not quite sure how to do the type information in a portable way though. But how about this: ``` scala val userdata = ArrayBuffer[Map[Any, Any]]() ``` Each 'client'...

The main requirement i can see is the C compiler for the emulator. If i wanted to run on windows i would start by getting sbt and scala working inside...

I don't have any say over this but I somewhat agree. I don't think UInt/Bundle, but definitely the test stuff I reckon and Util stuff (Complex + ChiselUtils). Issue with...

A separate chisel utils project looks like its coming (https://groups.google.com/forum/#!topic/chisel-users/pxRCGfFL_YQ) Perhaps Chisel 3 could break some compatibility and Chisel 2 remains supported with bug fixes. Not my decision though.

Is [this](https://github.com/ucb-bar/chisel/blob/master/src/main/scala/FPGA.scala) what you are looking for? As you indicate above the only difference is the "isInlineMem" flag. As to if it should be true or false, I think that...

This is related to #588 and #589 Essentially formatting of the output. I think the best way to do this is as #588 suggests and optionally make it silent. Can...

Hi, yeah I know the bit extract is redundant in this case. It was just a simplification of what I was actually trying to do. I am fine with leaving...

this issue seems solved. Following code working ``` scala @Test def issue99() { class BigUInt extends Bundle { val data = UInt(INPUT, 256) val oflo = Bool(INPUT) override def cloneType()...

I don't think T and C should have equivalence. Looking at src/test/resources/MultiClockSuite_Comp_1.v, this verilog is actually unsynthesizable as T0 is used for clock and temporary variable but passes the test.