crdavis12
crdavis12
Any chance of this being implemented? I also see #51 which sounds similar, but I can't see the full conversation. Looks like it's an older issue from Google Code.
No, I'm thinking more like dimensions on a drawing. The T_s and other labels at the top of @darkstar's diagram, that show time (or some other unit) between two events...
I've also just run into the issue of unaligned transfers not working in the `axi_read_slave`. Haven't gotten there yet but I suspect `axi_write_slave` will be similar. Is there any more...
~TODO: Need to update tests~
Any word on when this might be able to be merged? I heard something about breaking verification components out into a different repo -- planning to wait for that first?
@LarsAsplund -- any chance of getting this released as a 4.7.1 patch? We've had internal tools pointing to this branch for a while now but would be nice to get...
I would also get use out of this feature. One nice thing this would bring is integration into our CI system. Instead of simply showing passed/failed tests, this would allow...
I get a similar error in Riviera (2022.04). Specifically with mixed language simulation of `axi_axil_adapter` (my top level is VHDL). I can run the included testbench in the same version...