Christian Klarhorst

@enjoy-digital Could you please elaborate a bit more on what simplifications/improvements are not implemented/missing for S6DDRPHY? Is one of the missing features that S6DDRPHY doesn't use IDELAY/ODELAY for data alignment?

> NaxRiscv also increases the latency by one. > > Isn't increased by two ? as it add pipelining on both command and responses ? Yes by two :) >...

FYI: With early_wb_req=True, early_data_handover=True and the latex NaxRiscv master we are now at: ``` litex> mem_speed 0x10001000 0x500 Memspeed at 0x10001000 (Sequential, 1.2KiB)... Write speed: 641.6KiB/s Read speed: 730.5KiB/s ```...

Very nice to hear! Did you use the latest nax master and `early_wb_req=True, early_data_handover=True` ? With 100mhz? It seems to not reach timing on all boards I have, but I'm...

> --bus-standard axi-lite Nice, this one seems to always reach timing. Maybe because there are fewer converters used? Idk All in all, the axilite2wishbone converter is now more configurable. I...

Hey @francis2tm you said in your first post: > I looked around in the source and the only components that I think can contribute to the BRAM count are: ROM,...

I just run the `gsd_orangecrab` target on the current master branch. I found out that you need to use `--build` so that it compiles the software & hardware, otherwise the...

Hi @francis2tm #1409 should save you a few more BRAMs. > Since BIOS is only ran at startup time, is there any way of moving the BIOS to a flash...

(Sorry for the noise, I should stop using the master branch for pull requests :) )

I put the new parameter in `scala_args` and therefore thought that it will already be hashed. Looks like the `generate_netlist_name` will be called before the `add_memory_buses` func is called. I...