Chris Gyurgyik

Add function parameters to data flow analysis.

2

Addresses #120 .

[SSA] Ensure phi args are only added when defined.

5

Address latter part of #108. Originally, variables were added to `phi` that were undefined along the path. This resulted in `id`ing a non-existent variable during the `from_ssa` phase. I was...

Attempt at fixing copy propagation in LVN pass.

2

This is a first attempt at #77. It is far from elegant. This gist of the function is to: 1. Look for an instruction with `id` op. If `arg` has...

[DF] defined analysis producing wrong output.

1

### Example ``` # bril2json < p.bril | python3 ../../df.py defined @main(awesome_integer: int) { .entry: print awesome_integer; } ``` ### Actual: ``` entry: in: ∅ out: ∅ ``` ### Expected...

[StaticLogicToCalyx] Incorrect bound count in dot product.

6

```mlir // Original dot product. // RUN: circt-opt %s -lower-static-logic-to-calyx func.func @main() { %c0_i32 = arith.constant 0 : i32 %lhs = memref.alloc() : memref %rhs = memref.alloc() : memref %result...

[CIRCT] Lowering high level MLIR programs to Calyx.

8

This documents progress on lowering a high level program to native* Calyx and then through Cider. This should serve as a useful reference for those not entirely familiar with the...

Add icarus-verilog to test suite.

8

I think it would be a good idea to add a few tests (one specifically for `sqrt`) for the icarus-verilog backend. Perhaps benchmarks as well? This would require some additions...

`exp` operator producing negative values when `x` is a large negative number.

5

Program: ``` python3 calyx-py/calyx/gen_exp.py tests/correctness/exp/degree-4-signed.txt ``` Data: ``` { "x": { "data": [ -4000.0 ], "format": { "numeric_type": "fixed_point", "is_signed": true, "width": 32, "int_width": 16 } }, "ret": { "data":...

[library] Remove blocking statements.

2

From @rachitnigam in #750: > Generally recommend splitting up assignments an `always_comb` block so that only individual signals are assigned to. > > Instead of: > > ``` > always_comb...

Bit splitting in Calyx.

7

Sometimes we only want to access a certain subset of the bits in a multi-bit bus. `std_slice` provides limited functionality in this regard. For example, in SV, we could access...