Christopher Celio
Christopher Celio
**Summary:** A nice-to-have feature is the ability to enable and disable hardware features from the software. **Examples:** * Enable TSO memory consistency * Enable watchdog timer * Change predictor behaviors...
There needs to be some enforcement/requirements on the inputs into the hardfloat units (e.g., MulAddRecFN) to catch infinite loops during Chisel elaboration before they occur. In my particular use-case, the...
I'm experiencing a `java.lang.UnsupportedOperationException: empty.head` that is caused by a Reg(Vec()) of size 0. ``` scala val num_stages = 0 val r_valids = Reg(init = Vec.fill(num_stages) { Bool(false) }) ```...
**TL,DR: There needs to be a width check on signals before generating the final code.** --- I've found the following circuit generates erroneous Verilog code (I didn't check C++). It...
Although large priority encoders have been fixed in C++, a new test should be added to prevent regression as we move to chisel 3.0.
I'm not sure if this is supported or legal Chisel, but it is possible to write a Vec of a Vec and it will compile and run properly in C++...
The script continues on and attempts to "ls" and then copy over the run/ directories which don't exist.
All of the current tests cases used in (https://github.com/riscv/riscv-tests/blob/master/isa/rv64uf/fdiv.S) use the dynamic rounding mode. It would be nice if they also verified that static rounding modes set by the instructions...
It's easy to introduce a bug in the handling of SP instructions that are stored in 64-bit wide F registers, but the tests currently doesn't appear to check for DP...
https://github.com/freechipsproject/chisel-testers/wiki/Using%20the%20PeekPokeTester I've been reading the above documentation and it's not obvious to me how to use the verilator backend instead of the firrtl interpreter backend and how to get a...