Christopher Celio

> buggy branch predictor \o/ Spectre proof! Unfortunately yes, the BPU needs performance verification work and the secureboom work is still a work-in-progress.

Is this now resolved?

Is the test small and reproducible using the default Boom flow? If so, maybe we can take a look. However, if you have a fsdb file of the failure occurring,...

The new chisel3.util.experimental.BoringUtils may help here.

Providing the contents of `output/rv64ud-p-fsgnj.out` would be helpful, which will contain a more specific error message. However, the `enableCommitMapTable` option is unsupported and not a part of the regular regression...

That seems... unfortunate. Torture is a time-consuming pain to debug a failing case with, whereas the riscv-tests will throw an error code and you can jump to the source code...

BOOM has been taped-out in TSMC 28 nm HPM. The post-synthesis results were ~37 fan-out-of-4 and the post-place-and-route results were ~50 fan-out-of-4. This was performed using the MediumBoomConfig. There are...

> 1. This means that the frequency you reached was about 2 GHz? We used 28 nm HPM, which I don't think is quite as fast as you are quoting....

This is DefaultBoomConfig? Can you try MediumBoomConfig and see if you notice a difference? And can you give me the full path from: Startpoint: ExampleBoomSystem/tile/boom/core/iregister_read/exe_reg_uops_1_fu_code_reg_9/CP Endpoint: ExampleBoomSystem/tile/boom/core/issue_units_1/IssueSlot_13/slot_p1_reg/D I've not seen...

Okay thanks for the data, that looks a lot more like what I expect. First, you will almost certainly need to blackbox the integer register file. This is described a...