Robert Balas

Specifying remote cores

9

Let's say I have a testbench (a core itself) that requires three cores, each one not listed in the standard library but on available github. Each such core on github...

I think the intention is just to have a `doc/` folder.

Listing package twice in command list results in broken link in node crash

4

Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.) ```bash $ cat pkg.sv package pkg; endpackage $ cat top.sv module top import...

Single stepping through hardware loops doesn't work. ### Steps to Reproduce 1. git hash 6c858bca4559da3b191007ce2f1debeadbeb635e (master) Unfortunately, I don't have a minimized reproducible example at hand, but it was reported...

`sberror` is not signaled if `sbaccess` is invalid

10

We are supposed to signal `sberror` when the requested `sbaccess` is not supported (which currently is every type except the "native" bit width) See also https://github.com/pulp-platform/riscv-dbg/issues/57

Assuming a system with a 32-bit and a 64-bit core accessing the debug module over a 64-bit wide bus (`BusWidth=64` in the debug module). In that case we maybe don't...

It's not clear if and how you can run an RTL simulation of the core-v-mcu. Ideally, the README.md would explain how to do this.

In `riscv-tests/benchmarks/Makefile`, the ABI is [hardcoded](https://github.com/riscv-software-src/riscv-tests/blob/master/benchmarks/Makefile#L46) to `lp64d`. This causes `XLEN=32` builds to fail like this ```bash mkdir -p benchmarks make -C benchmarks -f /tmp/riscv-tests/benchmarks/Makefile src_dir=/tmp/riscv-tests/benchmarks XLEN=32 make[1]: Entering directory...

riscv/sim: Fix order of operations in fnmadd/fnmsub

4

Previously it was implicitely assumed that float operations are associative. We change the implementation to match exactly the given order in the spec. Fixes various gcc tests when running those...