Robert Balas
Robert Balas
@wallento Thanks for the detailed information. I'm quite new to fusesoc so I'm not sure I entirely understand your proposal, so let my re-express my thoughts again: * For each...
Same issue on android 10
@RTLhamster Until the official CORE-V GCC catches up, you could try PULP GCC (v2.4.0 based on gcc 9.2.0) here https://github.com/bluewww/riscv-gnu-toolchain/. We use it at ETH to compile for the cv32e40p....
@mmatzev fpnew does work with verilator. Fpnew for example is used in the ariane testbench, which supports verilator. There was a branch in this repo that added the FPU to...
Third issue should be fixed by this https://github.com/openhwgroup/cv32e40p/issues/384
If I understand it correctly then the only real hard constraint from the sw point of view is that after upstreaming to gcc the ABI is frozen.
PR is guaranteed to be broken with this merge https://github.com/openhwgroup/cv32e40p/pull/360. I believe a rebase is in order.
In modelsim you can check what the address of the illegal instruction is that should tell you already a lot of what is going wrong. Also this is not a...
Let me add my thoughts on this topic: I'm currently aware of several *manifest* formats that are going around: * [fusesoc's core files](https://fusesoc.readthedocs.io/en/latest/user/overview.html) (by OlofK, used by lowrisc) * `src_files.yml`...
I agree with all the points you have brought up, especially the namespacing is useful. This is a common pitfall in the C language too. One more point I'd like...