bala122
bala122
Hi @tcal-x , I've tried to profile some cfu-function calls for my accel. design and as well as for a "test-setup". I'm seeing some unusually high cycle times. For ex:-...
Hi @tcal-x , I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga. Are the memory resources used in synthesis restricted...
Hi, I just wanted to know if the perf_get_mcycle or mcycle64 function for profiling is accurate in giving cycle counts, because I tried it out with one of my custom...
I'm not sure about the procedure to add your own custom tflite model with CFU. Does this framework support custom ML models as well? I'm getting this issue when I...
Changes were made to all required files to add the custom "neural_net1" model to the menu list upon running the "make renode" command. The following error still persists: " CXX...
Hi @tcal-x and @mithro , I'm getting the following error on uploading to the arty A7 board upon running the make load command. This hasn't happened before and I'm not...
Hi @tcal-x and @mithro , In my network/model, I've noticed that there is a high memory bottleneck compared to computation time, so I wanted to try to use the cfu...
Hi @tcal-x and @mithro , I was trying to change certain parameters of the d-cache on the Vexriscv using the scala file ([](https://github.com/google/CFU-Playground/blob/main/soc/vexriscv/src/main/scala/vexriscv/GenCoreDefault.scala)). From the parameters, I can gather that...
Hi, @mithro and anyone else, I just wanted to know what the typical litedram port sizes are ( in bits I presume) since I need to figure out the L2...
Hi @alanvgreen , @tcal-x , I just wanted to know if theres any way in which we can force the synthesis tool to use BRAMs for certain specific cfu storage...