bala122
bala122
Thanks, @mithro
Hi @tcal-x , I just wanted to know if the Vexriscv core itself utilizes the ddr memory ( already physically present in the fpga) and the controller for interfacing with...
Okay, sure. Thanks @tcal-x
An update after looking at the disassemblies- I think perf_get_mcycle64() just increments after every instruction (if the pipelined Vexriscv core takes 1 cycle/instr on an avg) including the cfu_op instruction...
No actually Im trying to simulate on renode first. Is there a way to get cycle accurate simulation without a physical board ? ( using vivado maybe?)
I'm getting the following error: ``` %Error: /home/shivaubuntu/CFU-playground/ee18b155/CFU_Playground_Gitlab/proj/proj_nn_svhn/cfu.v:4: Cannot find include file: fp_mul.v `include "fp_mul.v" ^~~~~~~~~~ %Error: /home/shivaubuntu/CFU-playground/ee18b155/CFU_Playground_Gitlab/proj/proj_nn_svhn/cfu.v:4: This may be because there's no search path specified with -I. `include...
The above worked only after adding all modules into a single cfu.v file. Also, I just wanted to add that it would be helpful if you could post some details...
Hi, any updates on the cycle accurate info about the CFU bus interface? Any doc would be helpful. Thanks.
Hi, also just a query related to profiling- Are the memory access to DRAM or SRAM is modeled with a multi-cycle delay on verilator, or is any access to memory...
Hi, any update on the above? The only reasonable conclusion I could make out was that memory is modelled as a multi cycle delay even in simulation along with many...