Andy Wright

Issues with defined macros in bsvpreprocessor.py

3

Right now, the following is not supported in connectal/scripts/bsvpreprocess.py (code from lib/BSVSource/Contexts/Contexts.defines within the Bluespec installation directory): ``` `define SynthBoundary(mkM,IM) \ (*synthesize*)\ module [Module] mkM``V(Tuple2#(completeContextIfc,IM))\ provisos(Expose#(CompleteContext,completeContextIfc,_n));\ (*hide*)\ let _init

Reads and writes to illegal CSRs should raise an Illegal Instruction exception. Since the commit ca2b76e7ef5794ccc8190ce68395b3c0d278563f, reads to illegal (or unimplemented) CSRs return 0, and writes do nothing. Before that...

but it needs to at least 128 bits from mulh.

Internal signals don't work after Verilator update

1

pyverilator finds internal signals by parsing `VL_SIG*` lines in an `.h` file generated by verilator. The most recent version of verilator looks like it doesn't use the `VL_SIG*` macros anymore....

The test `test_pyverilator_finish_2_same_files` (https://github.com/csail-csg/pyverilator/blob/master/pyverilator/tests/test_pyverilator.py#L633-L692) fails because sim_1 and sim_2 both load the same shared object and the verilator `gotFinish` uses a global variable to track if the simulator has finished....

Columns in different summary tables with same name affect each other

3

I'm not sure if this is a bug report or an improvement suggestion because I don't know if this behavior is intended or not. To reproduce from a new document:...