WRoenninger

AXI4+ATOP on chip memory slave

5

This adds two modules: - `axi_to_mem`: Salve module, max throughout simultaneous read/writes 50%, read or write 100%. - `axi_to_mem_banked`: With enough banks 100% throughput with simultaneous reads/writes. Notes to Bender:...

This is a first WIP to update `axi_demux` according to #153. This is intended to be merged after #157 and sits on top of that branch. Same general changes regarding...

WIP: AXI_XBAR parameters

8

This is a first WIP to update `axi_xbar` according to #153. I also added and adapted the documentation that was in `doc/axi_xbar.md` for inline for auto generation. The doc file...

AXI_XBAR pipeline

5

This adds a change to the `axi_demux` implementation which has the benefit that the crossing AXI busses inside of `axi_xbar` can now be pipelined. The issue was that the `axi_demux`...

WIP: AXI4 Last Level Cache

3

Added AXI4 Last Level Cache Features: - Write back, Read and Write allocate - Parameterizable in set-associativity, line length and number of blocks - Adaptive scratch pad memory mapping of...

To revive the library discussion started in #55. For a lot of the VHDL designs I've seen recently, there was heavy usage of different libraries for each of the sub...

Truncation of `usage_o` port in `fifo_v3` when parameter `DEPTH` is a power of 2

2

The `usage_o` port of `fifo_v3` has currently a width of `$clog(DEPTH)`. This causes the pointer to wrap around to all zeros, if the FIFO has a power of 2 `DEPTH`...