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WIP: AXI4 Last Level Cache

Open WRoenninger opened this issue 6 years ago • 3 comments

Added AXI4 Last Level Cache Features:

  • Write back, Read and Write allocate
  • Parameterizable in set-associativity, line length and number of blocks
  • Adaptive scratch pad memory mapping of individual sets
  • Multiple open AXI transactions
  • Tag memory initialization BIST
  • Flush by user and SPM reconfiguration
  • Random replacement Added Documentation

This PR directly depends on changes from #116 and #115.

WRoenninger avatar Jan 11 '20 10:01 WRoenninger

Rebased onto current master.

WRoenninger avatar Dec 04 '20 17:12 WRoenninger

Vsim run script for axi_llc took on an Intel i7-4790 a little less than 7h to complete.

WRoenninger avatar Dec 08 '20 15:12 WRoenninger

Rebased onto current master for ci fix by #129.

Same ci timeout issue as for #115. Running vsim script for all modules takes around 8h.

WRoenninger avatar Dec 30 '20 15:12 WRoenninger

The AXI4 Last Level Cache (LLC) has been moved to a dedicated repository on pulp-platform: axi_llc

thommythomaso avatar Sep 01 '22 08:09 thommythomaso