VidyaChhabria
VidyaChhabria
@Colin-Holehouse @maliberty Is this something that check_power_grid should not be reporting as an error? Let me know if it needs a change.
Thanks for pointing it out. Sure I will be able to fix this. It needs a little bit of cleaning to the README and code. I am a little busy...
@animeshbchowdhury for timing paths, the clock pins on synchronous logic is typically a timing start point. Refer: https://anysilicon.com/the-ultimate-guide-to-static-timing-analysis-sta/ . You have clk2Q delay plus combinational logic to the end point...
@vikrg23 @bingyuew please comment on this. Is this because we do not have Python APIs for start and end point?
@vikrg23 can you help address?