NVlabs
Circuit OPS data expectation mismatch
Hi @liangrj2014, @agnesina , @VidyaChhabria
I'm working with the CircuitOPS data for the design 'GCD' and I found out some issues. I want to dig into the details to understand if the data itself is incomplete or something is wrong.
For e.g. In GCD, I found that the CLK pin of DFF is being considered as startpoint
https://github.com/NVlabs/CircuitOps/blob/2b56a3b32157e6070df8111282ce22b68f77a519/IRs/asap7/gcd/pin_properties.csv#L1092
But, in the actual synthesized netlist, I see something as follows:
Issue: First, I don't expect the CLK pin to be a startpoint, instead it is receiving input from clock PI. Is this a correctly annotated startpoint? Second, I expected the PI and PO to be part of startpoints and endpoints. Instead, I do only see the output of D flip flops as endpoints. Aren't POs considered as endpoint?
@animeshbchowdhury for timing paths, the clock pins on synchronous logic is typically a timing start point. Refer: https://anysilicon.com/the-ultimate-guide-to-static-timing-analysis-sta/ . You have clk2Q delay plus combinational logic to the end point which is D pin of FF.
The other type of timing startpoints are PI. Other types of endpoints are PO in addition to DFF pin. Is there absolutely no end point or start point that is a port? @vikrg23 can you check?
Got it, makes sense!
I didn't see any PI or PO ports which I was expecting to be part of start-point and endpoint. @vikrg23 can comment more once he cross-check.
@vikrg23 @bingyuew please comment on this. Is this because we do not have Python APIs for start and end point?
Hi @animeshbchowdhury ,
Since ports don’t have all the properties that pins do (like max_slew, max_cap), we hadn’t included them in pin_properties. We are now planning to add a new file called port_properties that lists all the PIs and POs along with their properties. Will update the CircuitOps scripts and dataset with these changes soon.
