Katharina
Hello. hdlConvertor does not support the parallel_case attribute. An example can be found here: https://github.com/KatCe/hdlConvertor_issue_185 Using the python script in the repo I tried all 3 language settings mentioned and...
Hello, the following module can not be parsed: ``` module minimized_in ( clk_i, rst_ni, use_sign_i, sign_i, result_o ); input wire clk_i; input wire rst_ni; input wire use_sign_i; input wire sign_i;...
Hello, the following file could not be parsed: https://github.com/KatCe/pyverilog_issue_125/blob/main/picorv32_sv2v_out.v Got the following error: ``` Pyverilog/pyverilog/vparser/parser.py", line 1589, in p_if_statement_woelse p[0].end_lineno = p[5].end_lineno AttributeError: 'ForStatement' object has no attribute 'end_lineno' ```...
## Observed Behavior A MULH instruction that is aborted by an unsolicited memory error response leaks information about its input values to a subsequent MUL instruction. The subsequent MUL instruction...
I have found a security vulnerability where the execution time is influenced by the data operand of an 'addi' instruction. The following test bench reproduces the problem. When setting the...
Hello, I have found a security vulnerability where an addi (or slti) instruction can unexpectedly write into the mtvec CSR and therefore manipulate the trap handler execution location unexpectedly. The...
When generating the default set of regression tests with the following command: ``` run --target=rv64gc --simulator=questa -o out_rv64gc ``` and using the spike isa simulator cloned from the link (https://github.com/riscv-software-src/riscv-isa-sim,...
Hello, morty version 0.9.0 fails with a parse error in the following code example: ``` // filename: inside_test.sv module test (bit clk); int a,b,c; bit d; if (a inside {b,...
## Observed Behavior If the top level data_gnt_i signal is either constantly high, or it is high at certain clock cycles (without an outstanding request), and a load is followed...