Bill94l

The mmu_sv39.elf fail with SocSim

18

Hi Charles, The mmu_sv39.elf fail with SocSim, here is the command I used ```Bash sbt "runMain naxriscv.platform.tilelinkdemo.SocSim --xlen 64 --nax-count 1 --load-elf ext/NaxSoftware/baremetal/mmu_sv39/build/rv64ima/mmu_sv39.elf --start-symbol _start --pass-symbol pass --trace" ``` According...

riscv tests with virtual memory enabled fail

3

Hi Charles, I generated tests with virtual memory enabled from the riscv-tests. When I start the tests from the "test_3" symbol, the execution finishes successfully, otherwise the execution fails when...

[BUG] CSR write verification error in the Verilator wrapper

5

Hi Charles, Following on from my previous issue https://github.com/SpinalHDL/NaxRiscv/issues/70#issuecomment-1910747595, where I had an error with the double and float tests using RVLS. I didn't understand why these tests didn't work....

RVLS and testsGen.py

6

Hello, 1) What is the difference between checking with these two methods which uses spike as a reference model? - testsGen.py: which generates a pass or fail for each test...

Hi, The attached code tries to read a `mhpmcounter23h` that is not implemented, on the spike side it throws an exception, but on the DUT side it commits because the...

Fix the check of the register Rd is not equal to zero for c.lwsp instruction and Update IO rang addresses

4

Hi, Please find the modification for c.lwsp below. Kindly make the necessary adjustments for the remaining compressed instructions that require a non-zero check of the RS and RD registers -...

storeFresh unused : trap-store_access_fault

5

Hi, After running a program generated by riscv-dv for rv64imafdc, accessing address 0x7fffff20 generates an exception (trap_store_access_fault) in spike, but the DUT does the commit and RVLS detects a commit...

A trap is triggered when the pmpcfg register is read by csrr

8

Hi Charles, Now I have RISCV-DV integrated with NaxRiscv. This allows me to do fuzzing by generating random programs and start lockstep execution with RVLS via SocSim. After running a...