Bill94l

Hi @farnam16 how did you connect the axi-lite with the corsbar (Xbar) ? Thnaks

Thank you so much @farnam16

Dear @farnam16 Could you take a look at my issue [https://github.com/openhwgroup/cva6/issues/703](url) which is to add a new IP on the bus, maybe you will have a suggestion? Thanks in advance

To be able to run and debug a software application in standalone on the CVA6 core, we used the RISC-V GNU Compiler for coss-compilation, once the binary is generated you...

Hello! - Did you follow all the steps mentioned in the README ? (especially the FPGA Emulation step) - Linux should work normally, did you change something in the hardware...

- You can use OpenOCD and GDB to make the compiled program start and run ([ take a look at #469 ](https://github.com/openhwgroup/cva6/issues/469)) - The binary is loaded from JTAG(not from...

- Yes, you should use the `riscv64-unknown-elf-gcc` - From #444 you would need to develop a BSP. ## BSP (Board Support Package) The **BSP** is a low-level software package that...

I ignored the missmatch by making a few changes to "hart.cpp" and adding a patch to spike "riscv/csrs.cc" to log the write operation in the FCSR register rather than in...

Hi, The code execution log using NaxRiscvRegression shows an exception during PMP initialization, but the code is executed successfully. [hart.cpp](https://github.com/SpinalHDL/rvls/blob/0cc9365bbc5764379a59caeca98f8bff379afd56/src/hart.cpp#L184) ```CPP void Hart::physExtends(u64 &v){ v = (u64)(((s64)v (64-physWidth)); } ```...

Dear Charles, Thank you for your quick reply. My ultimate goal is to build a lockstep verification environment based on NaxRiscv & RVLS into which I can integrate the RISCV-DV...