yongjoo
yongjoo
While building the `Hardware_Acceleration/Design_Tutorials/05-bottom_up_rtl_kernel/krnl_aes` project, I got some errors at the stage of FPGA logic optimization. My vitis version is 2021.2 and Ubuntu version is 18.04. I found some advice...
Hi I reproduce the project following under command lines ``` mkdir build cd build cmake ../ -DMM_DATA_TYPE=float -DMM_PARALLELISM_N=32 -DMM_PARALLELISM_M=8 -DMM_MEMORY_TILE_SIZE_N=512 -DMM_MEMORY_TILE_SIZE_M=512 -DMM_ADD_RESOURCE=FAddSub_nodsp -DMM_MULT_RESOURCE=FMul_nodsp make make hw ``` Then run like...
In Xilinx U250 product site, I can only access the latest platform version, not xilinx_u250_xdma_201830_2. Is there any plan for supporting the latest platform version?
Hi- I wanna take a look into the role of "enqueueMigrateMemObjects" during map/unmap buffer. So, I comment out "Send the buffer down to the Alveo card" section like below. ```...