Xiang W

> This last change nicely fixes the number of CSR reads/writes. Thanks. > > The code looks good. All the existing tests in riscv-tests/debug still pass. > > One remaining...

> @wxjstz, can you provide some example commands on how to set a hardware breakpoint that uses the new code? > > I'm not sure why you haven't responded to...

We have mailing list based patch review. You need to join mailing list: http://lists.infradead.org/mailman/listinfo/opensbi Then send this patches use "git send-email" Regards, Xiang W

[syscall normally return the number of bytes that are not written](https://github.com/openocd-org/openocd/blob/master/src/target/semihosting_common.c#L1365) semihosting_write in opensbi normally return the number of bytes that has been written semihosting_puts in opensbi normally return the...

> Its implementation complys with the convention of linux write opensbi not running on linux. It running on debugger. You need to know how this debugger implements syscall. Like this:...

XuanTie implements a strange SYS_WRITE. Is this weird stuff going to spread to all software?

@eosea @timsifive

RV32G/RV64G are general purpose platforms, G includes IMAFD_Zicsr_Zifencei. so general purpose platforms support Zifencei extensions, we may need to test if the target platform supports Zifencei or add the option....

Although Zifencei is an optional extension, it often appears, and only some simple embedded platforms do not need to implement this extension.

What I mean is: this patch introduces bugs and needs to be removed. Whether the Zifencei extension is supported is another question.