Wei Song (宋威)
Wei Song (宋威)
Since what bothered me most was the Tilelink and the deplomacy, I did not spend much time on the Rocket core itself. Feel free to contribute if you get any...
I set up this rocket-chip-read repo to comment on the Chisel code of the rocket-chip project. Although describing the underlying logic/thoery/mechanism of individual blocks is important, it does not fit...
That's because nothing has been done in there.
Nexys A7 (the 100T variant) should be identical to Nexys4DDR, at least according to Digilent. However, we do not have one at hand and can not verify. I agree with...
A normal boot should take less than a couple of minutes. So it does not look right. Have you strictly follow the instructions for compiling the kernel? Before trying any...
No, this is uncommon. It still smell like something unstable with the UART connection, although I have no clue about any potential cause.
This is probably because the UART is still polled by the driver. If it is replaced with a interrupt-based driver, the response time shoudl be improved. However, I am afraid...
The RoCC interface is pretty old and become absolete. I believe it has been removed form the Rocket-Chip (the upstream repo) for quite some time. We have not touched this...
@wallento Originally we though when trace debugger is enabled, trace printout can be replaced with instruction trace collected by trace debugger. However, the instruction trace nearly always buffer overflow. In...
Any update on this single 'H' problem?