wkkuna

Add `xc7z020clg484-1` part to artifacts

2

There seems to be support added in both [f4pga-arch-defs](https://github.com/SymbiFlow/f4pga-arch-defs/blob/main/xc/xc7/archs/zynq7_z020/devices/CMakeLists.txt#L1) and [prjxray-db](https://github.com/f4pga/prjxray-db/tree/master/zynq7/xc7z020clg484-1) but there are no artifacts for this part available. Is it possible to include `xc7z020clg484-1` part in `*xc7z020_test*` package?

<file>.v name appended to generated SV file when a blackbox is used

4

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** I came across this issue when bumping a project from Chisel 5.0 -> 6.2, I've tried to...

libs: ahb_slv_sif: Latch hsize on address phase

2

Accordingly to IHI0033A 3.4, `HSIZE` is of address bus timing. When two consecutive `NONSEQ` transfers (say A and B) of different `HSIZE` value are issued, the effective size of A...

Add multibit encoding for selected DCLS logic

3

* Adds multibit encoding for DCLS's: * `disable_corruption_detection_i` * `lockstep_err_injection_en_i` * `corruption_detected_o` * Adds `el2_mubi_pkg` that contains multibit encoding values & definitions for the operators * Adds configuration options &...

Newest version (2.3.0) breaks compatibility for python3.9