William E. Lamie

Hi Mark, Yuxin is with me over at rtosx.com (px5rtos.com).... I'll ask him tomorrow about this.

Hi Mark, I'm sorry about that... Hope to have some feedback early next week. Best regards, Bill On Fri, Feb 23, 2024 at 7:47 AM MarkAtBosch ***@***.***> wrote: > Hi...

Hi Mark, I've discussed this with Yuxin, and we believe what you proposed earlier in the thread is correct. Is your request simply that it needs be updated in the...

Not sure if this is what you are looking for, but ThreadX support for most processor architectures is composed of 8 assembly language functions in separate files (typically tx_*.s) and...

There is currently no ThreadX SMP support for the Cortex-M architecture. I'm part of RTOSX.com which does provide engineering services for such things. Please feel free to reach out if...

I see what you are seeing. It appears that the information in tx_api.h applies to building the C code. It appears that TX_ENABLE_EXECUTION_CHANGE_NOTIFY should be used when building the assembly...

How is the module being loaded via the module manager? Generally, ThreadX modules should be built in a PIC and PID fashion so the R9 data area address should be...

Taking the generic Cortex-A9 support to any specific processor of the same architecture is fairly straightforward. The biggest effort is to integrate the IRQ (and FIQ) interrupt handlers to match...

This is definitely possible... tx_thread_schedule.s, tx_thread_system_return.s, tx_thread_context_save.s, and tx_thread_context_restore.s are the likely places for the enhanced logic.

This is definitely a problem. A solution is to move RA into a compiler-preserved register (like S0) before the call. After the call returns, RA can be restored from the...