Wen-Heng (Jack) Chung

@seanpmorgan , @sunway513 and @parallelo would provide updates on this.

I second this request. Created an internal ticket SWDEV-180694 to track it. It'd be highly desirable to have this API implemented so machine learning frameworks can properly schedule available GPU...

relevant code in TensorFlow: https://github.com/ROCmSoftwarePlatform/tensorflow-upstream/blob/develop-upstream/tensorflow/core/util/gpu_launch_config.h#L165 Without this function implemented in HIP the grid / block size selection on AMD hardware would always be sub-optimal.

@sabreshao unfortunately due to current limitation in upstream LLVM AMDGPU backend, this feature is not supported yet.

@sabreshao sorry i wasn't clear. function pointer array is not supported yet. it's not possible to do indirect function calls with the current released version of LLVM AMDGPU backend.

I have one V1000 on my cube, and I do want to see embedded APU be put onto ROCm roadmap but unfortunately there is no ETA for this. Notice this...

@EvilPictureBook thanks. I didn't know kernel side of things may have been cleared up. Not so sure if CRAT table on BIOS for V1000 though. Say in case one's able...

Please review your test case first as there is no clear indication it's a bug in the compiler or runtime. Reviewing copy_log.txt we can see this kernel works fine: ```...

@david-salinas for apparent reasons I can't really be assigned to this ticket and drive it to conclusion J

@eukaryote31 Instead of trying to build TensorFlow on your own, is it possible to use docker images for you? Here are some prepared docker images: https://hub.docker.com/r/rocm/tensorflow/tags Or could you try...