Eugene Feinberg

Runny occamy simulations in xsim sometimes triggers 0 time simulation loops. One loop seems to be related to use of atop_filter and the massaging of ready/valid signals to downstream axi...

For simulation ordering and lint cleanliness assignments in always_comb blocks should not use non-blocking assignment.

Add fusion-compiler script generator

3

This PR adds basic support for Synopsys Fusion Compiler based on the older Synopsys target. The main initial difference is the use of absolute paths throughout the generated script as...

Internal error with structure initialization using default with custom type

2

(thank you for this fantastic tool) In using Verilator to link some systemverilog, I wanted to initialize some typedef'ed custom types that are buried a few layers of typing down...

Support for Cadence Xcelium simulator

1

Adds basic support for Cadence Xcelium simulator. Only verilog (not vhdl) tested.

Add .e as a variant of verilog for encrypted verilog

1

Some IP vendors distribute encrypted verilog IP as .e extension